Among the several issues that need to be taken into account in the deployment of the Next Generation Network, the clock recovery of the Time Division Multiplex (TDM) signals carried over packet networks is no doubt in the number of the most crucial and critical ones. Due to the not synchronous nature of present packet networks (e.g. Ethernet), the different methods today defined to recover the timing of TDM services exhibit a number of applications limits and synchronization quality problems that need to be addressed. In particular the packet delay variation (PDV) caused by the packet network has a big impact on the quality of the recovered clock in all the methods of timing recovery.
TDM networks are based upon a hierarchical timing distribution. One or more extremely accurate primary reference clocks are at the top of the hierarchy and with their Stratum 1 accuracy characteristics are suitable to provide reference timing signals to secondary clocks with Stratum 2 accuracy. Secondary clocks are then suitable to provide reference timing to Stratum 3 nodes implementing in this way the proper hierarchy of time synchronization required to meet the telecom network performance and availability requirements. This strict timing distribution scheme is designed to limit jitter and wander accumulation with the consequent negative impacts in terms of buffer under/overflow and relative service errors and unavailability.
When emulating TDM transport the packet delay variation (PDV) introduced by packet network may be mitigated by placing the TDM packets into a jitter buffer. The problem with this approach is that the ingress TDM source timing reference is not available on the egress side, and therefore the precise rate to use to clock out data from the jitter buffer and end-user equipment is not known.
Known methods of recovering TDM source timing in this scenario include adaptive methods, differential methods and network synchronous methods.
In the adaptive case ingress and egress Provider Edges have no access to the network clock and the service clock is carried asynchronously over the packet switched network (PSN).
In the differential and network synchronous methods the ingress and egress Provider Edges have access to the network clock and the service clock is carried asynchronously over the PSN in the former case and synchronous with the PSN in the latter one. Network synchronous and differential methods have good performance, but they put the problem of the reference timing distribution to all the end equipments.
Different approaches to obtain this goal include the use of primary reference clock (PRC, as defined in ITU-T G.811) distributed architecture such as atomic clocks or GPS receivers (this approach, however, could be very expensive) or master timing distribution to the end nodes.
A master timing distribution scheme can be achieved using a synchronous physical layer (e.g. synchronous Ethernet Physical Layer, or Synchronous Digital Hierarchy (SDH)), or via new emerging methods (e.g. IEEE 1588, Network Time Protocol—NTP).
Differential and adaptive methods allow the service clock transparency while in network synchronous scenarios the service clock is not preserved.
When timing transparency is required and no accurate reference timing is available in the end node the only alternative is to attempt the clock recovery process based exclusively on the circuit emulated TDM traffic (adaptive methods). These kinds of applications are very frequent and therefore it is very important to be able to handle the related timing issues.
By making reference to adaptive methods it is understood that the class of techniques used to recover the clock are based exclusively on the TDM circuit emulation traffic. This operation is possible taking into account that the source TDM device generates bits at a constant bit rate determined by its clock. These bits, however, are received in packets affected by the described negative effects of packet delay variation (PDV). As a consequence, the clock recovery task becomes a filtering and averaging process to negate the PDV effects and capture the original stream average rate.
Phase-locked loop (PLL) solutions are widely used to regenerate a clean clock able to approximate the original bit rate as much as possible.
Two known methods of adaptive clock recovery employs adapting a local clock (controlling the local PLL) that is based on the level of the receiver's jitter buffer or on the comparison of the packet arrival time with the expected arrival time.
Main problems of the adaptive PLL based methods known in the art are the convergence time required and the latency that the jitter buffer size involves. The convergence time is a consequence of long period of observation of the level position or packet arrival times the PLL needs before locking onto the source clock. The latency problem is a consequence of the jitter buffer size that has to be big enough to handle centering problems (the buffer level may settle far from the desired buffer center position) and lower the consequent probability of underflow/overflow.
In conclusion, the adaptive methods known in the art exhibit a strong dependency of the regenerated clock on the packet delay variation and convergence time and latency.